The present invention relates to a method of manufacturing a high integration semiconductor memory device, and more specifically, to a method of forming a buried word line included in a cell array of a semiconductor memory device.
A type of semiconductor memory device (e.g., DRAM) includes a plurality of unit cells each including a capacitor and a transistor. A double capacitor has also been used to temporarily store data. A transistor has been used to transmit data (i.e., read and write) between a bit line and a capacitor corresponding to a control signal (word line). The transistor includes a gate, a source and a drain. Charges between the source and drain move in response to a control signal inputted to the gate. The charges move through a channel region in accordance with the properties and operation of the transistor.
When a transistor is formed in a semiconductor substrate, a gate is formed in the semiconductor substrate, and impurities are doped at both sides of the gate to form a source and a drain. Due to an increase in data capacity and integration of a semiconductor memory device, the size of each unit cell is driven to be smaller. That is, the design rule (i.e., critical dimension) of the capacitor and the transistor included in the unit cell is decreased. As a result, a channel length of the cell transistor is made shorter, which causes a short channel effect and a drain induced barrier lowering (DIBL) effect that hinders a normal operation. For preventing the short channel effect and the DIBL effect, the doping concentration of the channel region has been increased to obtain a threshold voltage required in the cell transistor. However, as the design rule is decreased to less than 100 nm, the increase of the doping concentration in the channel region increases an electric field of a storage node (SN) junction degrading a refresh characteristic of the semiconductor memory device. In order to prevent the degradation of the refresh characteristic, a cell transistor having a three-dimensional structure is used. As a result, it is possible to secure a long channel length of the cell transistor vertically even as the design rule is decreased. Moreover, if the channel length of the cell transistor is secured, the doping concentration is decreased to prevent the degradation of the refresh characteristic.
Further, as a semiconductor memory device is more highly integrated, a distance between a word line and a bit line which are connected to the cell transistor becomes narrower. Thus, a parasitic capacitance between the word line and the bit line increases, and an operation margin of a sense amplifier which senses and amplifies data transmitted through the bit line is deteriorated. Finally, an operation reliability of the semiconductor memory device is degraded.
For reducing the parasitic capacitance between the word line and the bit line, a buried word line structure has been suggested. The buried word line structure means that a word line is completely buried in a semiconductor substrate. A conductive material made of the word line is deposited in only lower part of a recess formed in the semiconductor substrate, and an insulating material is formed in an upper part of the recess. Accordingly, the word line is formed at a lower level than the bit line formed on top of the semiconductor substrate surface. Thus, the word line may be clearly separated from the bit line by the insulating material.
FIGS. 1a to 1g are cross-sectional diagrams illustrating a method for fabricating a semiconductor device that has a buried word line structure in a general semiconductor apparatus.
Referring to FIG. 1a, a device isolation film 104 that defines an active region is formed over a semiconductor substrate 102 by a shallow trench isolation (STI) method. After an insulating film 105 is formed over the active region and the device isolation film 104, a recess 106 is formed. The recess 106 is used for forming a gate pattern after forming the device isolation film 104. Two recesses 106 are formed over one active region, and one recess 106 is formed over the device isolation film 104.
As shown in FIG. 1b, a conductive material is deposited with a given thickness so that the recess 106 may be filled with a conductive layer 108. The conductive layer 108 may include a metal material such as TiN. Unlike a recess gate, in the buried word line structure, the inside of the recess 106 does not include polysilicon but a metal material such as TiN, thereby securing a gate threshold voltage margin because of the different physical properties related to charge movement between metal and silicon.
Referring to FIG. 1c, a chemical mechanical polishing (CMP) process is performed on the conductive layer 108 to expose the upper portion of the insulating film 105.
Referring to FIG. 1d, an etch-back process is performed using an etching selectivity difference between the insulating film 105 and the conductive layer 108 to remove the upper portion of the conductive layer 108 in the recess 106. After the etch-back process, the insulating film 105 is removed.
As shown in FIG. 1e, a nitride film 110 is deposited over the semiconductor substrate 102 and the upper portion of the recess 106 where the conductive layer 108 is removed. An interlayer insulating film 112 is deposited over the nitride film 110. A patterning process is then performed using a mask that defines a bit line contact to etch a portion of the nitride film 110 and the interlayer insulating film 112. A contact hole 114 for forming a bit line contact is formed between the neighboring recesses 106 formed in the active region, that is, over a drain region.
Referring to FIG. 1f, after a conductive material is buried in the contact hole 114, a planarization process is performed to form a bit line contact 116.
Referring to FIG. 1g, a metal barrier film 118 is formed over the bit line contact 116, and a bit line 120 is formed over the metal barrier film 118. The bit line 120, the metal barrier film 118 and the bit line contact 116 are surrounded by an insulating film 122 so that they may be electrically separated from a storage node contact 124 formed over a source region.
The semiconductor device fabricated by the above process increases a physical distance between the bit line 120 and the conductive layer 108 used as a word line buried in the recess 106, thereby reducing a parasitic capacitance between the word line and the bit line that may degrade the reliability of the semiconductor device. However, due to the characteristic of the etch-back process performed on the conductive layer 108 shown in FIG. 1d, the conductive layer 108 disposed over the upper portion of the recess 106 is not completely removed and remains at the sidewalls of the recess 106. The conductive layer 108 disposed in the center of the recess 106 is removed corresponding to the etching depth. When the conductive layer 108 remains at the sidewalls of the upper portion of the recess 106, an electrical field may be concentrated in the conductive layer 108 that remains at the sidewalls of the recess 106 when a voltage is applied to the word line. When the semiconductor device is used as a cell transistor, the electrical field degrades the operating characteristic of the unit cell, and a leakage current generated by the electrical field shortens a data storage time.
If the conductive layer 108 disposed at the sidewalls of the upper portion of the recess 106 is not completely removed, the conductive layer 108 may be exposed when the contact hole 114 for forming the bit line contact 116 is formed. In this case, the bit line contact 116 and the conductive layer 108 may be electrically connected. This phenomenon may occur while the storage node contact 124 as well as the bit line contact 116 is formed. The generation of the junction defect (i.e., electrically connecting the conductive layer 108 used as a word line with the bit line contact 116 or the storage node contact 124) degrades the operating reliability of the semiconductor device.